This invention relates to a method and system for converting a highly autocorrelative digital video signal so that it can be recorded magnetically or optically on a recording medium which is weak in recording a d.c. signal or very low frequency signal.
Generally, in recording or reproducing digital codes, the d.c. component of the signal is often lost during the recording or reproducing process. To alleviate this impropriety a technique for converting (modulating) digital codes into a signal with little d.c. component needs to be applied in advance of recording. For example, in the digital VTR industry, there is known the method of reducing the d.c. component of a digital code signal by utilizing the correlation of pictures. A technique of inverting every second sample among sampled data is described in an article entitled "An Analytical Approach to the Standardization of Digital Videotape Recorders" by Jurgen K. R. Heitmann, SMPTE Journal, March 1982, pp. 230. U.S. Pat. No. 4,531,153 discloses a method which consists of two procedures (a) and (b) as follows.
(a) A sampled video signal digitized into a code is converted into another code by the table which is an ascending-order list of CDS (Code word Digital Sum), i.e., each bit of code is evaluated to be +1 for "1" or -1 for "0" and all bit values are summed up for each possible code. For example, when a single pixel of picture is expressed in an 8-bit code, there are a total of 256 possible codes including 1, 8, 28, 56, 70, 56, 28, 8, and 1 codes having CDS values of -8, -6, -4, -2, 0, 2, 4, 6, and 8, respectively. 8-bit codes of 256 kinds derived from the video signal are evaluated from 0 to 255 in decimal and converted by 1-to-1 correspondence into a Digital Sum Variation Check Code (DSVCC) of 256 kinds listed in ascending order. The variation in the amplitude of the video signal for each pixel causes little change in the CDS value of each converted code.
(b) The converted code signal is recorded on the tape in a period providing high correlation, e.g., by inverting the polarity of the recording signal at every other pixel. If two adjoining pixels in the input video signal are coded with the same CDS, two codes converted for the two pixels by this process have their d.c. components cancelling each other and they are eliminated. If two input codes have similar values, if not equal, their d.c. components are reduced by this process and made suitable for digital recording on the magnetic tape. However, although the method of the above patent application is effective for reducing the d.c. component in the code signal, the system is much affected by erroneous coding which would occur during the recording or reproducing process. In this respect, a video signal level having a value of `96` is to be converted into a binary code of `00011101` with DSV=0 as exemplified in the above patent publication. Let it be assumed that the 8th bit (LSB) is erroneously converted to "0" in the recording-reproducing process, resulting in `00011100`. This binary code corresponds to the original code with a value of `46`. Decimal values `96` and `46` are expressed in binary as `01100000` and `00101110`, respectively, and they differ in bits 2, 5, 6 and 7. Namely, a single bit error in the recording-reproducing process will result in a 4-bit error through the inverse conversion for the DSVCC code following the reproduction process. An error at the 8th bit (LSB) of a natural binary code creates a minimal 1-level error against the maximum level of `256`, whereas an erroneous value of `46` against a correct value of `96` results in a 50-level error (96-46=50). On assumption that original codes take values `0` through `255` with the same probability and, after conversion into DSVCC codes as described in the above patent application, are rendered erroneous at one of eight bits with a certain equal probability during the recording-reproduction process, calculation was conducted to evaluate on the average single bit errors of DSVCC in terms of the number of bits of the original codes and to evaluate corresponding error levels on the average. The result of calculation listed in the table (lower row) of FIG. 2a indicates that a single bit error in the DSVCC implies a 3.79-bit error with an error level of 50.27 in terms of the original code. If, on the other hand, the original natural binary code is recorded and reproduced without code conversion, a single bit error does not change its significance throughout the process and its mean error level is 31.88, i.e., (128+64+32+16+8+4+2+1)/8, as shown in FIG. 2a (upper row). Accordingly, the method disclosed in the above patent application involves the exacerbation of bit error degradation during the process, which amounts to 3.79 times the number of bits and 1.6 times in the error level as compared with the direct code handling system, in exchange for the reduction of the d.c. component in the recording signal.
Usually, error correction codes are used in digital video recording systems for the purpose of alleviating the influence of bit errors occurring in the recording or reproducing process. In most cases the error correction process takes place for the entirety of the 8-bit code of the video signal. Because of greater significance of a higher-order bit error acting upon the picture quality, error correction is stressed on the higher-order bits in some cases. An ultimate case is where a high grade error correction is implemented only for the high-order 4 bits, with the low-order 4 bits being left uncorrected. A question arising in this case is that when the input video signal is digitized into a code, which is appended by an error correction code and recorded in the DSVCC coding system, which is followed, after reproduction, by inverse conversion to the original code and then the error correction process, how an error occurring in the recording or reproducing process influences the high-order 4 bits of the inversely converted code. Another matter to be considered is about the probability of error at any of the high-order 4 bits of the inversely converted code when any one of 8 bits has failed in the recording or reproducing process. In the preceding example of the input code having a decimal value of `96` which is spoiled at the LSB with a result of inverse conversion as `46`, the high-order 4-bit block includes an error bit at bit 2. The same calculation is conducted for the remaining 7 bits of the binary code `00011101` (which has been obtained by the conversion from decimal 96). The result of calculation for the 256 8-bit codes (decimal 0-255) is listed in the table of FIG. 2a (rightmost column). Direct handling of the natural binary code in the recording-reproduction process causes an equal probability of 0.5 for the occurrence of a bit error in the high-order 4-bit block and in the low-order 4-bit block, whereas the DSVCC coding system mentioned above causes the higher-order 4-bit block to include bit error(s) with a probability of 0.96. In other words, a bit error occuring at any bit position of an 8-bit code during the recording-reproduction process will result in bit error(s) in the high-order 4-bit block of an inversely converted code with a 96% probability. Generally, error recovery by the error correction code system is nullified when the number of data words including bit error(s) reaches a certain proportion, and therefore the range of error correction by the DSVCC coding system is narrowed with the increase in the number of error bits.